What is the difference between ANSI and IEC logic gate symbols?

ANSI / IEEE Std 91 distinctive-shape symbols use a different outline for each gate, such as the rounded AND and the pointed OR. IEC 60617-12 symbols use a rectangle for every gate and put a qualifier inside: & for AND, ≥1 for OR, =1 for XOR. Both describe the same logic, and IEEE Std 91 also includes the rectangular style.

What does the small circle on a logic gate mean?

The circle is the negation indicator. It inverts the signal at that pin, so an AND with a circle on the output is a NAND, an OR with a circle is a NOR, and a buffer with a circle is a NOT. A small triangle is a different mark, the polarity indicator, which shows a pin that is active at a low level.

What does ≥1 mean inside an IEC gate symbol?

It means the output is 1 when at least one input is 1, which is the OR function. The & in an AND symbol means all inputs must be 1, and =1 in an XOR symbol means exactly one input is 1.

Why are NAND and NOR called universal gates?

Every other gate can be built from NAND gates alone, or from NOR gates alone. Joining the two inputs of a NAND makes a NOT, and a NAND followed by that NOT makes an AND. The page shows AND built from two NAND gates and OR built from two NOR gates, with computed truth tables.

How many rows does a truth table have?

Two to the power of the number of inputs. A two-input gate has 4 rows, a three-input gate has 8, and a four-input gate has 16. NOT and a buffer have one input, so their tables have 2 rows.

Can I download or print the symbols and the chart?

Yes. Every symbol on the page can be downloaded as SVG or PNG, and the full eight-gate chart can be downloaded as PNG or SVG or printed on one landscape page. It is free to use and needs no account.

Electronics Reference

Logic Gate Symbols and Truth Tables

Chart of AND, OR, NOT, NAND, NOR, XOR, XNOR and buffer symbols in ANSI/IEEE and IEC styles, with Boolean expressions, truth tables, PNG, SVG and print.

ANSI / IEEE 91 and IEC 60617-12 symbols side by sideBoolean expression and computed truth table for every gateSVG and PNG download for each symbolPrintable one-page chart, no sign-up

Try the inputs

Set A and B once. Every card below highlights the matching truth table row and shows the output.

NOT and BUFFER have one input and use A only.

AND gate

Output: 1 only if all inputs are 1

ANSI / IEEE 91

IEC 60617-12

Boolean expression

Y = A · B
Y = AB
Y = A AND B

With the inputs above, Y = 0

AND gate truth table
A	B	Y
0	0	0
0	1	0
1	0	0
1	1	1

OR gate

Output: 1 if any input is 1

ANSI / IEEE 91

IEC 60617-12

Boolean expression

Y = A + B
Y = A OR B

With the inputs above, Y = 1

OR gate truth table
A	B	Y
0	0	0
0	1	1
1	0	1
1	1	1

NOT gate

Output: inverts the input

ANSI / IEEE 91

IEC 60617-12

Boolean expression

Y = A′
Y = ¬A
Y = NOT A

With the inputs above, Y = 0

NOT gate truth table
A	Y
0	1
1	0

NAND gate

Output: 0 only if all inputs are 1

ANSI / IEEE 91

IEC 60617-12

Boolean expression

Y = ¬(A · B)
Y = (A · B)′
Y = A′ + B′

With the inputs above, Y = 1

NAND gate truth table
A	B	Y
0	0	1
0	1	1
1	0	1
1	1	0

NOR gate

Output: 1 only if all inputs are 0

ANSI / IEEE 91

IEC 60617-12

Boolean expression

Y = ¬(A + B)
Y = (A + B)′
Y = A′ · B′

With the inputs above, Y = 0

NOR gate truth table
A	B	Y
0	0	1
0	1	0
1	0	0
1	1	0

XOR gate

Output: 1 if the inputs differ

ANSI / IEEE 91

IEC 60617-12

Boolean expression

Y = A ⊕ B
Y = A′B + AB′

With the inputs above, Y = 1

XOR gate truth table
A	B	Y
0	0	0
0	1	1
1	0	1
1	1	0

XNOR gate

Output: 1 if the inputs match

ANSI / IEEE 91

IEC 60617-12

Boolean expression

Y = ¬(A ⊕ B)
Y = AB + A′B′

With the inputs above, Y = 0

XNOR gate truth table
A	B	Y
0	0	1
0	1	0
1	0	0
1	1	1

BUFFER gate

Output: passes the input through

ANSI / IEEE 91

IEC 60617-12

Boolean expression

Y = A

With the inputs above, Y = 1

BUFFER gate truth table
A	Y
0	0
1	1

Printable logic gate chart

All eight gates on one landscape page: ANSI and IEC symbols side by side, Boolean expressions and truth tables. Download it or print it for a lab bench or a revision sheet.

Scroll sideways on small screens. Downloads are 2828 by 2000 px PNG or scalable SVG.

NAND and NOR are universal gates

Any Boolean function can be built from NAND gates alone, or from NOR gates alone, which is why chips and teaching kits stock so many of them. The trick is the inverter: tie both inputs of a NAND or NOR together and it becomes a NOT gate. Each example below is two gates in a chain, and the table next to it is computed from the circuit, then compared row by row with the gate it should equal.

AND from two NAND gates

The first NAND gives (A · B)′. The second NAND has both inputs tied to that signal, so it acts as a NOT and restores A · B.

AND from two NAND gates truth table
A	B	n	Y	AND
0	0	1	0	0
0	1	1	0	0
1	0	1	0	0
1	1	0	1	1

Y matches the AND column on all 4 rows

OR from two NOR gates

The first NOR gives (A + B)′. The second NOR has both inputs tied together, so it inverts that signal and gives A + B.

OR from two NOR gates truth table
A	B	n	Y	OR
0	0	1	0	0
0	1	0	1	1
1	0	0	1	1
1	1	0	1	1

Y matches the OR column on all 4 rows

The two symbol standards, side by side

ANSI / IEEE Std 91 (distinctive shape): each gate has its own outline. AND has a flat back and a rounded front, OR has a curved back and a pointed front, and XOR adds a second curved line behind the OR body. A triangle is a buffer. This is the style most US textbooks, data sheets and circuit simulators use.
IEC 60617-12 (rectangular shape): every gate is a rectangle, and a qualifier inside it names the function. "&" means AND, "≥1" means OR (at least one input is 1), "=1" means XOR (exactly one input is 1), and "1" means a single-input element. IEEE Std 91 and its supplement 91a also define this rectangular style, which is why the two standards share the same qualifiers.
Inversion: a small circle on the output, called the logic negation indicator, turns a gate into its inverted version. NOT is a buffer with a circle, NAND is AND with a circle, NOR is OR with a circle, and XNOR is XOR with a circle. This chart uses the circle everywhere. A small triangle, the polarity indicator, is a different mark that says a pin is active at a low level, and it is not used here.

How to read a truth table

A truth table lists every combination of input values and the output each one produces. With two inputs there are four rows, and with n inputs there are 2 to the power n rows. Every table on this page is computed in code by running the gate’s Boolean function over all input combinations, not typed in, so the rows always match the expression shown next to it. Use the A and B buttons above the cards to see one row light up on every gate at once. For example, with A = 1 and B = 0, AND gives 0, OR gives 1, XOR gives 1 and NAND gives 1.

Boolean expressions and De Morgan’s laws

Each card lists the common ways to write the gate’s function: a dot or no sign for AND, a plus sign for OR, a prime or the ¬ sign for NOT, and ⊕ for XOR. Two identities connect the gates. The NAND of A and B equals NOT A OR NOT B, and the NOR of A and B equals NOT A AND NOT B. These are De Morgan’s laws, and they are why a NAND gate is drawn as either an AND with a circle on the output or an OR with circles on the inputs in some diagrams. Both forms mean the same thing.

Why NAND and NOR are called universal gates

A set of gates is universal if every Boolean function can be built from it. NAND alone is universal, and so is NOR alone. Tying the two inputs of a NAND together gives a NOT. A NAND followed by that NOT gives AND. Feeding inverted inputs into a NAND gives OR. NOR works the same way with the roles of AND and OR swapped. This is why many logic families, and many exam questions, ask you to rebuild a circuit using only one gate type. The two worked examples above are drawn and checked by the page itself.

Sources and what this chart does not cover

Symbols are drawn from scratch for this page after the standards IEEE Std 91-1984 with supplement 91a-1991, and IEC 60617-12 (binary logic elements, now kept in the IEC 60617 database). The standards themselves are not reproduced. IEC also defines "=" as the equivalence qualifier (output 1 when all inputs are equal). For two inputs it matches "=1" with an output circle, which is how XNOR is drawn here, but with three or more inputs the two differ, so this chart sticks to the two-input form. The chart covers the eight basic gates with one or two inputs. Gates with more inputs, flip-flops, multiplexers and other IEC elements are outside its scope.